1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device provided with at least one of a via and an interconnect.
2. Description of the Related Art
Semiconductor devices currently available are generally provided with semiconductor elements such as a transistor, a resistance, a capacitance and soon formed on a semiconductor substrate, an interconnect formed among dielectric layers on the semiconductor element, and a via which connects the semiconductor element and the interconnect.
FIG. 10 is a schematic cross-sectional view showing a constitution of a semiconductor device. Here, a constitution of a semiconductor element is not shown in the drawing.
As shown in FIG. 10, the semiconductor device is provided with a first interconnect 114 formed on an underlying dielectric layer 110 provided on a semiconductor substrate 100, a second interconnect 136 isolated from the first interconnect 114 by an interlayer dielectric layer, and a via 134 which electrically connects the first interconnect 114 and the second interconnect 136.
The first interconnect 114 is formed in a first etch-stopper layer 112 and a first interlayer dielectric layer 113. The via 134 is disposed in a second etch-stopper layer 116 and a second interlayer dielectric layer 118. The second interconnect 136 is formed in a third etch-stopper layer 138 and a third interlayer dielectric layer 140.
An upper face of the second interconnect 136 is covered with a metal diffusion barrier 142 which prevents diffusion of a metal contained in the interconnect. Over the second interconnect 136, a bonding pad (not shown in the drawings) for electrical connection to outside the semiconductor device and a protection layer 144 for preventing intrusion of moisture are provided.
To form the interconnect and the via the Damascene process is known, which includes filling an interconnect trench or a via hole with a conductive layer containing a metal such as copper (Cu), and scraping an excessive portion of the conductive layer by a CMP (Chemical Mechanical Polishing) process. In the Damascene process, an electrolytic plating process may be employed for filling an interconnect trench or a via hole with a conductive layer, as disclosed in JP-A Laid Open No. 1999-097391. The electrolytic plating process will be described below.
FIG. 11 is a block diagram showing a constitution of an electrolytic plating apparatus employed for the electrolytic plating process. In the subsequent passages, not only an independent piece of semiconductor substrate constituted of silicon or gallium arsenide, but also a semiconductor substrate on which a semiconductor element or an interconnect is formed will be collectively defined as a wafer. Also, the electrolytic plating apparatus will be employed to form a copper layer.
As shown in FIG. 11, the electrolytic plating apparatus is provided with a wafer holder 12 for holding a wafer W to be plated, a plating bath 14 in which a plating solution D is deposited, an anode 16 set so as to confront the wafer W which acts as a cathode, a power unit 18 for supplying a current between the wafer W and the anode 16, a voltmeter/ammeter 20 for measuring a voltage and a current between the wafer W and the anode 16, and a control unit 22 which controls a current to be supplied between the wafer W and the anode 16 as well as a voltage to be applied between the wafer W and the anode 16. The electrolytic plating apparatus is also provided with a carrier robot (not shown in the drawings), which attaches the wafer W to the wafer holder 12 and dips it in the plating solution D, and then removes the wafer W from the wafer holder 12 after completion of the plating process. The plating solution D is, for example, copper sulfate containing a trace of additive.
The wafer to be plated is provided with a barrier metal layer and a copper seed layer, formed in this sequence on a predetermined opening pattern on a dielectric layer surface. When an operator places such wafer W on a designated inlet/outlet gate, the carrier robot (not shown in the drawings) of the electrolytic plating apparatus attaches the wafer W to the wafer holder 12 and dips it in the plating solution D. Thereafter, the control unit 22 monitors a value of the voltmeter/ammeter 20 to control the power unit 18 such that a predetermined current is supplied between the wafer W and the anode 16, by which a copper-plated layer is formed on the opening pattern.
A method of manufacturing the above semiconductor device will be described.
FIGS. 12A to 12C and 13D to 13F are schematic cross-sectional views progressively showing a method of manufacturing the semiconductor device. Here, it is to be construed that the semiconductor substrate is provided with semiconductor elements though they are not shown in the drawings, and such elements will not be particularly referred to in the following description.
After forming a semiconductor element (not shown in the drawings) on the semiconductor substrate 100 shown in FIG. 10, the underlying dielectric layer 110 is formed. The first etch-stopper layer 112 and the first interlayer dielectric layer 113 for insulating the first interconnect 114 are formed on the underlying dielectric layer 110. Then a known lithography and etching process is carried out to form a predetermined first trench pattern in the first etch-stopper layer 112 and the first interlayer dielectric layer 113, after which the first trench pattern is filled with a conductive layer, and the first interconnect 114 is formed through the Damascene process. Thereafter, a second etch-stopper layer 116 is formed over an upper face of the first interconnect 114, and then the second interlayer dielectric layer 118 and an anti-reflection layer 120 are sequentially formed. Then a known lithography process is carried out to form a resist 124 having a via hole pattern 122 (FIG. 12A).
Referring to FIG. 12B, anisotropic etching is performed to remove a portion of the anti-reflection layer 120, the second interlayer dielectric layer 118 and the second etch-stopper layer 116 that is not covered with the resist 124, to thereby form a via hole 126. Thereafter the resist 124 and the anti-reflection layer 120 are removed by ashing and a stripper.
Then referring to FIG. 12C, a barrier metal layer 130 containing tantalum is formed on an upper face of the second interlayer dielectric layer 118 and on the via hole 126 to prevent diffusion of copper. After that, a copper seed layer 132 is formed as a base of plating growth of copper. Then the wafer W is loaded on the electrolytic plating apparatus shown in FIG. 11, and a current of a predetermined current density is supplied between the wafer W and the anode 16 so that the plating process is performed.
FIG. 14 is a graph showing a current supplied between the wafer and the anode during the electrolytic plating process. The horizontal axis represents a duration of plating time after starting the process, and the vertical axis represents a current value.
As shown in FIG. 14, upon starting the electrolytic plating process, current of a constant value is supplied for a predetermined duration of time for forming the copper-plated layer. The current value in this case is approx. 1.0 to 5.0 ampere.
Through such plating process, a copper layer 133, in which the copper seed layer 132 has been merged, is formed as shown in FIG. 13D. Then a CMP process is performed to polish the copper layer 133 and the barrier metal layer 130 until an upper face of the second interlayer dielectric layer 118 is exposed, to thereby form a via 134. Thereafter a third etch-stopper layer 138 is formed to cover an upper face of the via 134, and a third interlayer dielectric layer 140 is formed (FIG. 13E).
Referring to FIG. 13F, the Damascene process is carried out as with the first interconnect 114, to form a second interconnect 136 constituted of a conductive layer filled in a predetermined second trench pattern formed on the third etch-stopper layer 138 and the third interlayer dielectric layer 140. Then a metal diffusion barrier 142 is formed over the second interconnect 136, after which a bonding pad (not shown in the drawings) is formed and then the protection layer 144 shown in FIG. 10 is formed.
According to such method of forming a copper-plated layer in a via hole, a cathode-side voltage is applied to an edge of the wafer that is in contact with the wafer holder 12. Accordingly, a voltage difference emerges between a border region and a central region of the wafer because of a resistance existing on the way from the edge to the center of the wafer, resulting in a lower bottom-up performance (degree of growth of copper from a bottom portion of a via hole) in a central portion compared with an border region. This may lead to defective filling of a copper layer in a via hole. Hereunder, description about the bottom-up performance will be given.
FIG. 15 is a schematic cross-sectional view showing a via hole for explaining the bottom-up performance.
When forming a copper-plated layer by an electrolytic plating process on a wafer having a barrier metal layer and a seed layer provided after forming a via hole 152 in a dielectric layer 150, a formation rate of the copper-plated layer is different between a bottom portion of the via hole 152 and an upper face of the dielectric layer 150. Referring to FIG. 15, when “a” stands for a formation rate of the copper layer at an upper face of the dielectric layer 150 and “b” that at a bottom portion of the via hole 152, a bottom-up ratio can be defined as b/a, according to which the greater the bottom-up ratio is the more entirely the via hole becomes filled with copper, in other words, the higher bottom-up performance is achieved.
A filling defect of copper in a central portion of a wafer becomes particularly prominent in case where the plating growth is inhibited by oxidation of the seed layer or impurity such as an organic substance that has adhered thereto. This is because an increase of a resistance on the way from an edge to a center of the wafer further lowers an effective voltage in a central portion of the wafer, thereby enlarging the unfavorable influence originating from a drop of a voltage applied between the wafer and the anode. Accordingly, the copper layer does not sufficiently grow in a central portion of the wafer during an initial stage of the plating process, resulting in a poorer filling performance of copper in the via hole compared with a border region of the wafer. Besides, an increase of wafer dimensions and reduction in thickness of a seed layer due to a progress in micronization further increase a resistance from an edge to a center of the wafer, thereby degrading a copper filling efficiency in a central region of the wafer.
Also, because of a difference in bottom-up performance between a border region and a central region of a wafer, in-plane uniformity of a copper layer thickness is impaired.
Further, in case where an electrolytic plating apparatus is provided with a plurality of plating baths, variation of a current value among the plating baths may affect a growth rate of copper in an initial stage of the plating process. This comes from the method of supplying a current based on a voltage control because a current value cannot be monitored, when dipping wafers in the plating solution. Here, since a current value in such a case is very small the variation of the current value among the plating baths becomes relatively large, and resultantly a difference in bottom-up performance and copper filling efficiency among the plating baths becomes more prone to be produced.